1. Field of the Invention
The present invention relates generally to test circuitry and circuit checking systems. More particularly, the present invention relates to a system and method for determining the exclusivity of signals as required for multiplexer select lines.
2. The Prior Art
The use of multiplexers (also referred to as xe2x80x9cMUXESxe2x80x9d) in complex circuitry is known in the art. Also known is the need to ensure signal exclusivity in multiplexers amongst the plurality of selection lines indicated for each multiplexer. That is, given a plurality of select lines to a multiplexer, only one such select line may be active or xe2x80x9chotxe2x80x9d at a given time. In the event of a failure regarding this rule, that is, more than one select line active in the multiplexer simultaneously, adverse circuit conditions will likely be the result (i.e. short between power and ground, or high current conditions in the circuit, resulting in damage or xe2x80x9cburnoutxe2x80x9d in circuit devices, as well as the circuit outputting undesirable results).
One way to avoid such problems in the prior art was to carefully design such circuits to avoid multiple select line simultaneous operation. However, as circuits become increasingly complex, including literally thousands of multiplexers in the overall circuit, theoretical circuit design controls become inherently inadequate. Furthermore, manually checking such circuits, one multiplexer at a time, during circuit testing is both time-consuming and woefully inadequate.
To overcome these and other shortcomings of the prior art, disclosed herein is a system for testing multiplexer select line exclusivity in a fast, efficient, and comprehensive manner. By employing a gate circuit and checking the output of that circuit, one or all multiplexers in a circuit may be singularly or comprehensively analyzed for xe2x80x9chotxe2x80x9d multiplexer exclusivity. That is, the system disclosed hereinafter applies a gate circuit appropriately to a multiplexer and then, via a series of processes, analyzes whether that multiplexer passes a test for select line exclusivity.
Such a process may proceed multipexer by multiplexer through a given circuit subunit, unit, or through a plurality of units coupled to a plurality of input/output devices. Since the process is automated, it may step from one multiplexer to the next in a subunit. Alternately, it may analyze all multiplexers within a subunit, or all multiplexers in all associated subunits within a unit. Furthermore, this process can also analyze whole units containing subunits, or multiple units as necessary. Simply put this system is not limited by prior art constraints such as predefined circuit topology. Rather, as is desirable, all related circuit elements, multiplexers, may be evaluated individually or together to achieve the broadest circuit multiplexer testing in less time than heretofore possible.